"IDE - hardware reference & information document" - читать интересную книгу автора (Ivopol A.)

-RESET
is asserted for at least 25 microseconds after voltage levels
have stabilized during power on and negated thereafer unless
the drive needs to be reset at a later time.

D0...D15
bidirectional data bus. D0...D7 are used during 8 bit data
transfers e.g. registers and ECC bytes.

KEY
is not a connection. The connection pin is missing and forms
part of a mechanism that prevents the IDC connector from being
reverse connected.

-IOW
is the Write strobe signal. The rising edge of -IOW clocks data
from from the host to the drive.

-IOR
is the Read strobe signal. The falling edge of -IOR enables
data from the drive onto the host data bus.

-IOCHRDY
is negated to extend the host transfer cycle of any host
register read/write access when the drive is not ready to
respond to a data transfer request. When not negated, it is in
a high impedance state.

SPSYNC
spindle synchronization. This may be either input or output to
the drive depending on a vendor defined switch. If a drive is
set to MASTER the signal is output and if a drive is SLAVE the
signal is input. There is no requirement that each drive
implementation be plug compatible to the extent that a multiple
vendor drive subsystem be operable. However if drives are
designed to match the following recommendations then
controllers can operate drives with a single implementation:

There can only be one MASTER drive at a time in a
configuration. The host or the drive designated as master can
generate SPSYNC at least once per revolution (it may be more
than onceper revolution).

SPSYNC received by a drive is used as the synchronization
signal to lock the spindles in step. The time to achieve
synchronization varies and is indicated by the drive setting
DRDY. If the drive does not achieve synchronization, it will
not set DRDY.

A master drive or a host generates SPSYNC and transmits it. A